FIG. 1 shows a block diagram of a multi-port memory device 100 which may be a multi-port DRAM (dynamic random access memory) device for example. The multi-port memory device 100 includes a first port 102, a second port 104, a first memory bank 106, a second memory bank 108, a third memory bank 110, a fourth memory bank 112, and an access controller 114.
The first memory bank 106 is dedicated for access just by a first data processor (not shown) via the first port 102. The third and fourth memory banks 110 and 112 are dedicated for access just by a second data processor (not shown) via the second port 104. The second memory bank 108 has shared access by the first and second data processors via the first and second ports 102 and 104, respectively.
Just one of the ports 102 and 104 has access to the shared memory bank 108 at any given time. The access controller 114 arbitrates access to the shared memory bank 108 between the ports 102 and 104. On the other hand, the first port 102 has access to its dedicated bank, i.e., the first memory bank 106, at any time. Similarly, the second port 104 has access to its dedicated banks, i.e., the third and fourth memory banks 110 and 112, at any time.
FIG. 2 illustrates how refresh starvation may result in the multi-port memory device 100 of FIG. 1 with a timing diagram of signals. Referring to FIGS. 1 and 2, the authority controller 114 generates an authority signal that indicates which of the ports 102 and 104 is authorized for access to the shared memory bank 108. In FIG. 2, each of the first and second ports 102 and 104 generates CBR (CAS (column address strobe) before RAS (row address strobe)) commands to the shared memory bank 108. Each CBR command is issued for instructing the shared memory bank 108 to execute an auto-refresh command.
In FIG. 2, CBR commands are issued by the ports 102 and 104 when the port does not have authority for access to the shared memory bank 108. Thus, the auto-refresh command is not executed in the shared memory bank 108 resulting in refresh starvation in the shared memory bank 108.
FIG. 3 is a timing diagram for further illustrating such refresh starvation in the shared memory bank 108. Referring to FIGS. 2 and 3, the first memory bank 106 executes all of the CBR commands from the first port 102. Similarly, each of the third and fourth memory banks 110 and 112 executes all of the CBR commands from the second port 104.
The shared memory bank 108 executes a CBR command from the first or second port 102 or 104 when such a CBR command is issued with proper authority for access to the shared memory bank 108. Thus, unauthorized CBR commands (outlined in dashed lines with an X in FIG. 3) from the first and second ports 102 and 104 are not executed by the shared memory bank 108.
Thus in the example of FIG. 3, each of the dedicated banks 106, 110, and 112 executes seven auto-refresh commands. However, the shared memory bank 108 executes only five auto-refresh commands. Such lower number of auto-refresh operations performed in the shared memory bank 108 may result in refresh starvation with the memory cells not having sufficient charge for proper operation.
FIG. 4 shows a timing diagram of signals during operation of the memory device 100 of FIG. 1 for preventing refresh starvation. Referring to FIG. 4, each of the data processors coupled to the ports 102 and 104 generates a respective CBR command immediately before transition of port authority. Thus, a refresh operation is performed in the shared memory bank 108 immediately around each transition of port authority.
The timing diagram of FIG. 5 is similar to FIG. 3 but with the additional refresh operations 120 being performed in the shared memory bank 108 near each transition of port authority. In FIG. 5, a total of ten refresh operations are performed in the shared memory bank 108 compared to a total of five refresh operations in FIG. 3. Although refresh starvation is thus prevented in FIG. 5, execution of each refresh operation requires time and power consumption. Thus, performing a refresh operation in the shared memory bank 108 at each transition of port authority may result in slow operation and high power consumption in the memory device 100.
Thus, a mechanism for preventing refresh starvation with fewer refresh operations in a shared memory bank of a multi-port memory device is desired.